The present invention relates to the field of data processing systems and more particularly to architectures in small systems.
Since introduction of the IBM Personal Computer in 1981, there has been an increasing interest in small systems. Typically, the small system includes a system unit, including a central processor and main storage, and includes various input/output (I/O) units such as a keyboard, a display, a printer and a disk memory.
Small systems, like large systems, are under the control of software in various forms. The paramount control is the operating system (OS) which functions as the interface between application programs and the hardware. The portion of the software concerned with I/O devices is known as the basic input/output system (BIOS).
The BIOS typically includes self-test routines, device-handling routines, and system-service routines. The self-test routines are diagnostic instructions that are executed to ensure the correct operation and reliability of the system. The device handling routines coordinate and enable the functioning of input/output devices. Each I/O device includes a corresponding device-handling routine. Each routine consists of instructions for a specific set of functions for the I/O device including checking to see if the device is ready, causing data to be transferred from and to the device, and verifying the proper completion of the data transfer operation.
The system service routines provide essential services for the system such as loading, memory size determination, equipment determination, time-of-day, and print-screen functions.
In many systems, each I/O device includes a device controller. For example, a display unit typically includes a display controller, a disk unit includes a disk controller and when direct memory access (DMA) is employed, a DMA controller is provided.
In small systems, usually all of the I/O devices connect to a common I/O bus. Only one device at a time has access to the common bus.
Typically, direct memory access (DMA) is performed, a disk unit requiring a transfer to the system sends a request to the disk controller. The disk controller in turn sends a request to the DMA circuitry which in turn sends a request to the central processor. The central processor then returns an acknowledge signal to the DMA controller. At the same time that the acknowledge is sent to the DMA controller, the central processor stops all other activity on the bus. At that point in time, the DMA controller completes the direct memory access without any further involvement of the central processor. In small systems with only a single memory bus, the processor remains idle during DMA transfers.
The reason that the central processor gives up control to the DMA controller is to increase the speed of memory accesses. The DMA controller is capable of executing the control commands much faster then if the central processor since the central processor must execute a plurality of time-consuming instructions to achieve the same control function. Effectively the DMA controller is a co-processor specializing in making direct memory accesses.
The typical processing steps for communication between the central processor system and a disk, involve execution by the central processor of an I/O instruction. When the I/O instruction is decoded, a command is issued which will initiate operations with the I/O device. Typically, two types of commands are employed, a read command and a write command. Either the read command or the write command is issued to the disk controller. When the disk controller has a disk ready signal, the disk controller initiates the DMA request to the DMA control circuitry. The previous description of what happens when a disk controller requests a DMA operation was described above. After the DMA operation is completed, the disk controller signals completion by sending a transfer complete signal to the central processor. At that time, the central processor again commences executing instructions.
The difficulty with the conventional DMA circuitry is that substantial wasted time occurs during the period when the DMA requests are transmitted to the central processor and the central processor stops activity on the bus. For each DMA request, typical systems waste 30% of the time in making the DMA handshake.
In order to avoid this wasted time, there is a need for an improved system which more efficiently handles DMA requests.
Additionally there is a need for improved systems which require fewer components without need for a different controller for every I/O device.
In data processing systems, employing common buses, a priority scheme must be employed to determine which device will gain access to the bus when there is contention for bus access by more than one device. Many priority schemes have been employed for resolving contention among competing devices. In small systems, with only one I/O bus, only one device can gain priority to the bus at any given time. Frequently, the central processing unit is given lowest priority so that when direct memory access occurs between a disk and main storage, for example, when the central processing unit sits idle. It is desirable, even in small systems, to permit the central processing unit to perform useful functions even when priority or access to one bus in the system has been allocated to another device.
In small scale systems, elaborate priority schemes are usually not cost justified and therefore there is a need for an improved, a simple priority scheme which keeps the cost of resolving contentions among competing devices to a simple and economical level.